Design and Test of Computers: Advances in Functional Validation through Hybrid Techniques. / IEEE, IEEE Computer Society y IEEE Circuits and Systems Society
Tipo de material:
Recurso continuoIdioma: Inglés Detalles de publicación: Nueva Jersey, Estados Unidos: IEEE Computer Society 2007Descripción: v. ; 27cmISSN: - 0740-7475
- D457
Contenidos:
110-Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. 112-A Survey of Hybrid Techniques for Functional Verification. 124-Hybrid Verification of Protocol Bridges. 132-Combining Theorem Proving with Model Checking through Predicate Abstraction. 140-Hybrid, Incremental Assertion-Based Verification for TLM Design Flows. 154-Hybrid Approach to Faster Functional Verification with Full Visibility. 164-Economic Aspects of Memory Built-in Self-Repair. 174-Roundtable: Envisioning the Future for Multiprocessor SoC. 184-FSA SiP Market and Patent Analysis Report. 193-On the cusp of a validation wall
| Tipo de ítem | Biblioteca actual | Colección | Signatura topográfica | Copia número | Estado | Código de barras | |
|---|---|---|---|---|---|---|---|
Publicación Periódica
|
Biblioteca Rafael Meza Ayau | Hemeroteca | D457 2007 (Navegar estantería(Abre debajo)) | 01 | Disponible | 39641 |
110-Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. 112-A Survey of Hybrid Techniques for Functional Verification. 124-Hybrid Verification of Protocol Bridges. 132-Combining Theorem Proving with Model Checking through Predicate Abstraction. 140-Hybrid, Incremental Assertion-Based Verification for TLM Design Flows. 154-Hybrid Approach to Faster Functional Verification with Full Visibility. 164-Economic Aspects of Memory Built-in Self-Repair. 174-Roundtable: Envisioning the Future for Multiprocessor SoC. 184-FSA SiP Market and Patent Analysis Report. 193-On the cusp of a validation wall
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