Design and Test of Computers: Design and Test of RFIC Chips. / IEEE, IEEE Computer Society y IEEE Circuits and Systems Society

Colaborador(es): Tipo de material: Recurso continuoRecurso continuoIdioma: Inglés Detalles de publicación: Nueva Jersey​, Estados Unidos: IEEE Computer Society, 2008Descripción: v. ; 27 cmISSN:
  • 0740-7475
Tema(s): Clasificación CDD:
  • D457
Contenidos:
6-Guest Editors' Introduction: The Evolution of RFIC Design and Test. 10-Design and Analysis of a Transversal Filter RFIC in SiGe Technology. 18-Design of a Low-Noise UWB Transceiver SiP. 29-Decreasing Test Qualification Time in AMS and RF Systems. 38-Light-Enhanced FET Switch Improves ATE RF Power Settling. 44-Time-Division-Multiplexed Test Delivery for NoC Systems. 52-Low-Impact Processor for Dynamic Runtime Power Management. 64-Hybrid-SBST Methodology for Efficient Testing of Processor Cores. 76-Simultaneous Switching Noise: The Relation between Bus Layout and Coding. 88-In Conversation with Tensilica CEO Chris Rowen.
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6-Guest Editors' Introduction: The Evolution of RFIC Design and Test. 10-Design and Analysis of a Transversal Filter RFIC in SiGe Technology. 18-Design of a Low-Noise UWB Transceiver SiP. 29-Decreasing Test Qualification Time in AMS and RF Systems. 38-Light-Enhanced FET Switch Improves ATE RF Power Settling. 44-Time-Division-Multiplexed Test Delivery for NoC Systems. 52-Low-Impact Processor for Dynamic Runtime Power Management. 64-Hybrid-SBST Methodology for Efficient Testing of Processor Cores. 76-Simultaneous Switching Noise: The Relation between Bus Layout and Coding. 88-In Conversation with Tensilica CEO Chris Rowen.

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