Design and Test of Computers: Design and Test of RFIC Chips. / IEEE, IEEE Computer Society y IEEE Circuits and Systems Society
Tipo de material:
Recurso continuoIdioma: Inglés Detalles de publicación: Nueva Jersey, Estados Unidos: IEEE Computer Society, 2008Descripción: v. ; 27 cmISSN: - 0740-7475
- D457
Contenidos:
6-Guest Editors' Introduction: The Evolution of RFIC Design and Test. 10-Design and Analysis of a Transversal Filter RFIC in SiGe Technology. 18-Design of a Low-Noise UWB Transceiver SiP. 29-Decreasing Test Qualification Time in AMS and RF Systems. 38-Light-Enhanced FET Switch Improves ATE RF Power Settling. 44-Time-Division-Multiplexed Test Delivery for NoC Systems. 52-Low-Impact Processor for Dynamic Runtime Power Management. 64-Hybrid-SBST Methodology for Efficient Testing of Processor Cores. 76-Simultaneous Switching Noise: The Relation between Bus Layout and Coding. 88-In Conversation with Tensilica CEO Chris Rowen.
| Tipo de ítem | Biblioteca actual | Colección | Signatura topográfica | Copia número | Estado | Código de barras | |
|---|---|---|---|---|---|---|---|
Publicación Periódica
|
Biblioteca Rafael Meza Ayau | Hemeroteca | D457 2008 (Navegar estantería(Abre debajo)) | 01 | Disponible | 40900 |
6-Guest Editors' Introduction: The Evolution of RFIC Design and Test. 10-Design and Analysis of a Transversal Filter RFIC in SiGe Technology. 18-Design of a Low-Noise UWB Transceiver SiP. 29-Decreasing Test Qualification Time in AMS and RF Systems. 38-Light-Enhanced FET Switch Improves ATE RF Power Settling. 44-Time-Division-Multiplexed Test Delivery for NoC Systems. 52-Low-Impact Processor for Dynamic Runtime Power Management. 64-Hybrid-SBST Methodology for Efficient Testing of Processor Cores. 76-Simultaneous Switching Noise: The Relation between Bus Layout and Coding. 88-In Conversation with Tensilica CEO Chris Rowen.
No hay comentarios en este titulo.
Iniciar sesión para colocar un comentario.
2251-8215
