Design and Test of Computers: The Current State of Test Compression. / IEEE, IEEE Computer Society y IEEE Circuits and Systems Society
Tipo de material:
Recurso continuoIdioma: Inglés Detalles de publicación: Nueva Jersey, Estados Unidos: IEEE Computer Society 2008Descripción: v. ; 27 cmISSN: - 0740-7475
- D457
Contenidos:
112-Guest Editors' Introduction: Progress in Test Compression. 114-Historical Perspective on Scan Compression. 122-VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. 132-UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. 142-Hierarchical Test Compression for SoC Designs. 150-Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers. 160-Wireless System for Microwave Test Signal Generation. 168-An Illustrated Methodology for Analysis of Error Tolerance. 178-Device Model for Ballistic CNFETs Using the First Conducting Band. 188-Discussing DRAM and CMOS Scaling with Inventor Bob Dennard.
| Tipo de ítem | Biblioteca actual | Colección | Signatura topográfica | Copia número | Estado | Código de barras | |
|---|---|---|---|---|---|---|---|
Publicación Periódica
|
Biblioteca Rafael Meza Ayau | Hemeroteca | D457 2008 (Navegar estantería(Abre debajo)) | 01 | Disponible | 41147 |
112-Guest Editors' Introduction: Progress in Test Compression. 114-Historical Perspective on Scan Compression. 122-VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. 132-UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. 142-Hierarchical Test Compression for SoC Designs. 150-Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers. 160-Wireless System for Microwave Test Signal Generation. 168-An Illustrated Methodology for Analysis of Error Tolerance. 178-Device Model for Ballistic CNFETs Using the First Conducting Band. 188-Discussing DRAM and CMOS Scaling with Inventor Bob Dennard.
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